EFFECT OF GATE-OXIDE DEGRADATION ON ELECTRICAL PARAMETERS OF SILICON AND SILICON CARBIDE POWER MOSFETS

The power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is recognized as a crucial component of many power-electronic systems. The physical structure of both Silicon and Silicon Carbide power MOSFETs require an oxide layer as a dielectric material between their gate terminal and the semiconductor surface. The gate-oxide material, which is predominantly silicon dioxide, slowly degrades under the presence of an electric field. Over time, the degradation process significantly alters the electrical parameters of power MOSFETs, causing a negative impact on performance, reliability, and efficiency of power converters they are used in. In order to monitor this, the electrical parameters are utilized as precursors (or failure indicators) of gate-oxide degradation.Despite extensive investigation of gate-oxide degradation in Silicon (Si) power MOSFETs, the research literature has not attributed a consistent variation pattern to its gate-oxide degradation precursors. This dissertation investigates the variation pattern of existing precursors: a) threshold voltage, b) gate-plateau voltage, and c) on-resistance. While confirming the previously reported dip-and-rebound variation pattern of the threshold voltage and the gate-plateau voltage, a similar dip-and-rebound variation pattern is also identified in the on-resistance of Si power MOSFETs. Furthermore, a new online precursor of gate-oxide degradation— the gate-plateau time, is proposed and demonstrated to exhibit a similar dip-and-rebound variation pattern. The gate-plateau time is also shown to be the most sensitive online precursor for observing the rebound phenomenon. In addition, the analytical expressions are derived to correlate the effect of gate-oxide degradation with simultaneous dip-and-rebound variation pattern in all four precursors. The dip-and-rebound variation pattern is experimentally confirmed by inducing accelerated gate-oxide degradation in two different commercial Si power MOSFETs. While multiple electrical parameters have been identified as precursors for monitoring the gate-oxide degradation in Si MOSFETs, very few precursors have been proposed for Silicon Carbide (SiC) power MOSFETs. This dissertation proposes that in addition to the threshold voltage, the other online precursors identified for Si power MOSFETs: the gate-plateau voltage and the gate-plateau time, are also effective for monitoring the effect of gate-oxide degradation process in SiC power MOSFETs. Though the gate-oxide material is the same in both Si and SiC power MOSFETs, the effect of gate-oxide degradation on the variation pattern of electrical parameters is different. In contrast to the dip-and-rebound variation pattern of precursors in Si MOSFETs, the research literature has attributed a consistent linear-with-log-stress-time variation pattern to the threshold-voltage shift in SiC power MOSFETs. It is shown that both the gate-plateau voltage and the gate-plateau time increase in a linear-with-log-stress-time manner similar to the threshold voltage. The analytical expressions are derived to correlate the effect of gate-oxide degradation with simultaneous linear-with-log-stress-time variation pattern in all three online precursors. The increasing trend of precursors is experimentally confirmed by inducing accelerated gate-oxide degradation in both planar and trench-gate commercial SiC power MOSFETs under high voltage, high temperature, and hard-switching conditions.