As wireless communication standards evolve, radio frequency (RF) transmitter (TX) systems with higher linearity and wider bandwidth at increased output power (POUT) are required to meet the high demand for faster communication speeds and increased data traffic. Meanwhile, mobile and wearable applications require a smaller form factor and low-cost solutions. Low power consumption is also critical for increased battery life, which improves user experience. Digital TX is a promising architecture for a small area and low power consumption because conventional TX sub-blocks, such as digital-to-analog converter (DAC), mixer, driving amplifier, and power amplifier (PA), can be merged into a single block. Furthermore, the linearity, area, and power consumption of a digital TX can be significantly enhanced with the evolution of complementary metal oxide semiconductor (CMOS) technology that provides faster operation and finer segmentation at lower power dissipation. It is easy to migrate to the next generation CMOS process because the digital TX mostly comprises digital circuits. These advantages are more critical when there are multiple TXs in a single system, such as multi-standard and multi-in multi-out systems. A switched-capacitor (SC) PA or an SC RFDAC is employed as a base architecture in this study, ideally providing 100% peak efficiency as a segmented switching-mode PA; further, unlike conventional PAs, it does not suffer from a large output signal swing that modulates output impedance, causing amplitude and phase nonlinearities.This study demonstrates various architectures and design techniques for compact, highly efficient, and highly linear digital TXs. The contributions of this study are as follows:First, a watt-level highly efficient and highly linear quadrature digital TX with a dual-supply Class-G quadrature IQ-cell-shared SCPA architecture is proposed, which maximizes the POUT and efficiency of the quadrature digital TX. To enable the Class-G operation in the quadrature IQ-cell-shared SCPA architecture, a merged-cell-switching technique is proposed. Linearization techniques for the Class-G operation are proposed to compensate for the amplitude and phase mismatches between the two Class-G modes.Second, a compact and highly linear quadrature digital TX based on quadrature IQ-cell-shared SC RFDAC with linearization techniques is proposed; the linearization techniques increase the TX dynamic range by improving the TX linearity in both high and low POUT regions. Impedance linearization techniques for the output stage and an offset mid-tread code mapping technique improve the TX linearity in the high and low POUT regions, respectively. The area and power consumption of the RFDAC are minimized by sharing sub-circuits between the two RFDAC cells.Finally, a multimode multi-efficiency-peak SCPA architecture is proposed to maximize power back-off (PBO) efficiency in a polar digital TX. The multimode operation is achieved through an efficient combination of the dual-supply Class-G, Doherty, and 2-way time-interleaving techniques, thus, maximizing the PBO efficiency by introducing six efficiency peaks down to 18-dB PBO. A single-supply current-reuse Class-G switch is proposed for the highly efficient Class-G operation without any additional power management unit. Moreover, a LO-signal-restoration technique is presented to minimize both the power dissipation and area for the LO signal distribution.
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